HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 817

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3.5
The E-DMAC outputs the receive FIFO overflow alert signal (ARBUSY) to the EtherC to support
flow control function conforming to IEEE802.3x of the EtherC. The ARBUSY signal
synchronized with the bus clock (B clock) signal is also output to an external pin of this LSI.
When the capacity of data received in receive FIFO or the number of receive frames reach the
threshold (RFF2 to RFF0, or RFD2 to RFD0) specified in FCFTR in E-DMAC, ARBUSY is
valid.
The threshold is the value less than the overflow value: 2048 − 64, 1792 − 32, 1536 − 32,
and 256 − 32 bytes.
Figure 19.9 shows the configuration of the receive FIFO overflow alert signal (ARBUSY) output.
As shown in figure 19.9, because the ARBUSY signal passes through the system clock
synchronization circuit, it is behind the receive FIFO overflow alert signal received in EtherC.
Receive FIFO Overflow Alert Signal (ARBUSY)
This LSI
Figure 19.8 Configuration of ARBUSY
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
E-DMAC0
E-DMAC1
synchronization
Receive FIFO overflow
alert signal
Receive FIFO overflow
alert signal
System clock
ARBUSY
circuit
Rev. 1.00 Dec. 27, 2005 Page 773 of 932
EtherC
REJ09B0269-0100