HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 82

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
2.3.4
The control registers (SR, GBR, SSR, SPC, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The control registers are described below.
Status Register (SR): The status register (SR) indicates the system status as shown below. The
SR register can be accessed only in privileged mode.
Rev. 1.00 Dec. 27, 2005 Page 38 of 932
REJ09B0269-0100
Bit
31
30
29
Bit Name

MD
RB
Control Registers
Initial
Value
0
1
1
R/W
R
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Processing Mode
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling state.
Register Bank
The general registers R0 to R7 are banked registers. The
RB bit selects a bank used in the privileged mode.
0: Selects bank 0 registers. In this case, R0_BANK0 to
1: Selects bank 1 registers. In this case, R0_BANK1 to
The RB bit is set to 1 in reset or exception handling state.
R7_BANK0 and R8 to R15 are used as general
registers.
R0_BANK1 to R7_BANK1 can be accessed by the
LDC or STR instruction.
R7_BANK1 and R8 to R15 are used as general
registers.
R0_BANK0 to R7_BANK0 can be accessed by the
LDC or STR instruction.