HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 328

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 9 User Break Controller
Table 9.3
3. When the data value is included in the break conditions on channel B:
4. Access by a PREF instruction is handled as read access in longword units without access data.
5. If the L bus is selected, a break occurs on ending execution of the instruction that matches the
Rev. 1.00 Dec. 27, 2005 Page 284 of 932
REJ09B0269-0100
Access Size
Longword
Word
Byte
This means that when address H'00001003 is set in the break address register (BARA or
BARB), for example, the bus cycle in which the break condition is satisfied is as follows
(where other conditions are met).
Longword access at H'00001000
Word access at H'00001002
Byte access at H'00001003
When the data value is included in the break conditions, either longword, word, or byte is
specified as the operand size of the break bus cycle register B (BBRB). When data values are
included in break conditions, a break is generated when the address conditions and data
conditions both match. To specify byte data for this case, set the same data in two bytes at bits
15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B
(BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. Set the
word data in bits 31 to 16 in BDRB and BDMRB when including the value of the data bus as a
break condition for the MOVS.W @-As,Ds, MOVS.W @As,Ds, MOVS.W @As+,Ds, or
MOVS.W @As+Ix,Ds instruction (bits 15 to 0 are ignored).
Therefore, if including the value of the data bus when a PREF instruction is specified as a
break condition, a break will not occur.
break condition, and immediately before the next instruction is executed. However, when data
is also specified as the break condition, the break may occur on ending execution of the
instruction following the instruction that matches the break condition. If the I bus is selected,
the instruction at which the break will occur cannot be determined. When this kind of break
occurs at a delayed branch instruction or its delay slot, the break may not actually take place
until the first instruction at the branch destination.
Data Access Cycle Addresses and Operand Size Comparison Conditions
Address Compared
Compares break address register bits 31 to 2 to address bus bits 31 to 2
Compares break address register bits 31 to 1 to address bus bits 31 to 1
Compares break address register bits 31 to 0 to address bus bits 31 to 0