HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 387

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
10
9
8
7
6
5
Bit Name
DPRTY1
DPRTY0
DMAIW2
DMAIW1
DMAIW0
DMAIWA
Initial
Value
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
DMA Burst Transfer Priority
Specify the priority for a refresh request/bus mastership
request during DMA burst transfer.
00: Accepts a refresh request and bus mastership request
01: Accepts a refresh request but does not accept a bus
10: Accepts neither a refresh request nor a bus mastership
11: Reserved (Setting prohibited)
Wait States between Access Cycles when DMA Single
Address is Transferred
Specify the number of idle cycles to be inserted after an
access to an external device with DACK when DMA single
address transfer is performed. The method of inserting idle
cycles depends on the contents of DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted
Method of Inserting Wait States between Access Cycles
when DMA Single Address is Transferred
Specifies the method of inserting the idle cycles specified
by the DMAIW1 and DMAIW0 bits. Clearing this bit will
make this LSI insert the idle cycles when another device,
which includes this LSI, drives the data bus after an
external device with DACK drove it. When the external
device with DACK drives the data bus continuously, idle
cycles are not inserted. Setting this bit will make this LSI
insert the idle cycles even when the continuous accesses
to an external device with DACK are performed.
during DMA burst transfer
mastership request during DMA burst transfer
request during DMA burst transfer
Rev. 1.00 Dec. 27, 2005 Page 343 of 932
Section 12 Bus State Controller (BSC)
REJ09B0269-0100