HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 590

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Dec. 27, 2005 Page 546 of 932
REJ09B0269-0100
Bit
7
Bit Name
ER
Initial
Value
0
R/W
R/(W)*
Description
Receive Error
Indicates that a framing error or parity error
occurred during reception.*
0: No framing error or parity error occurred during
[Clearing conditions]
•
•
1: A framing error or parity error occurred during
[Setting conditions]
•
•
Notes: 1. The ER flag is not affected and retains
reception
reception
Power-on reset or manual reset
When 0 is written to ER after reading ER = 1
When the SCIF checks whether the stop bit at
the end of the receive data is 1 when reception
ends, and the stop bit is 0*
When, in reception, the number of 1-bits in the
receive data plus the parity bit does not match
the parity setting (even or odd) specified by the
O/E bit in SCSMR
2. When the stop length is 2 bits, only the
its previous state when the RE bit in
SCSCR is cleared to 0. When a receive
error occurs, the receive data is still
transferred to SCFRDR, and reception
continues.
The FER and PER bits in SCFSR can
be used to determine whether there is a
receive error in the data read from
SCFRDR.
first stop bit is checked for a value of 1;
the second stop bit is not checked.
1
2