HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 278

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 7 X/Y Memory
via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and
cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,
several cycles are necessary (the number of necessary cycles varies according to the ratio between
the internal clock (Iφ) and bus clock (Bφ) or the operation state of the DMAC and E-DMAC). In a
program that requires high performance, it is advisable to access the X/Y memory from space P2
or Uxy.
The relationship described above is summarized in table 7.2.
Table 7.2
[Legend]
7.3.4
In sleep mode, I bus master modules such as the DMAC and E-DMAC cannot access the X/Y
memory.
7.3.5
If writing that may causes an address error is performed on the X/Y memory, the contents of the
X/Y memory are not guaranteed.
Rev. 1.00 Dec. 27, 2005 Page 234 of 932
REJ09B0269-0100
CCR1.CE
0
0
1
1
Sleep Mode
Address Error
A:
B:
C:
X:
Setting
MMU and Cache Settings
MMUCR.AT
0
1
0
1
Accessible (recommended)
Accessible
Accessible (Note that MMU page attribute must be specified as cache disabled
by clearing the C bit to 0.)
Not Accessible
P0, U0
B
B
X
C
Logical Address Space and Access Enabled or Disabled
P1
B
B
X
X
P2, Uxy
A
A
A
A
P3
B
B
X
C