HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 64

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 1 Overview and Pin Function
Rev. 1.00 Dec. 27, 2005 Page 20 of 932
REJ09B0269-0100
Classification
Clock
Operating mode
control
System control
Symbol
XTAL
CKIO
CKIO2
MD5 to MD0
RESETP
RESETM
STATUS1
STATUS0
BREQ
BACK
I/O
O
I/O
O
I
I
I
O
I
O
Name
Crystal
System clock
System clock
Mode set
Power-on reset When low, the system enters the
Manual reset
Status output
Bus request
Bus request
acknowledge
For connection to a crystal
Supplies the system clock to
Supplies the system clock to
These pins set the operating
Low when an external device
Function
resonator. For examples of crystal
resonator connection and external
clock input, see section 11, On-
Chip Oscillation Circuits.
external devices. This pin can be
also used for external clock input.
external devices.
mode. Do not change values on
these pins during operation.
MD2 to MD0 set the clock mode,
MD4 and MD3 set the bus-width
mode of area 0, and MD5 sets the
endian.
power-on reset state.
When low, the system enters the
manual reset state.
Indicates that this LSI is in
software standby mode, reset, or
sleep.
requests the release of the bus
mastership.
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which
has output the BREQ signal that it
has acquired the bus mastership.

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