HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 837

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.3
The H-UDI has the following registers. Refer the section 23, List of Registers, for the addresses
and access size for registers.
• Bypass register (SDBPR)
• Instruction register (SDIR)
• Boundary scan register (SDBSR)
• ID register (SDID)
22.3.1
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined but
SDBPR is initialized to 0 if the TAP is in Capture-DR state.
22.3.2
SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is
initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-
UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in
this register.
Pin Name
ASEBRKAK
AUDSYNC
AUDATA3 to 0
AUDCK
Register Descriptions
Bypass Register (SDBPR)
Instruction Register (SDIR)
Input/Output
Output
Output
Output
Output
Description
Dedicated emulator pin
Section 22 User Debugging Interface (H-UDI)
Rev. 1.00 Dec. 27, 2005 Page 793 of 932
REJ09B0269-0100