HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 40

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 3.20
Table 3.21
Table 3.22
Table 3.23
Table 3.24
Table 3.25
Table 3.26
Table 3.27
Table 3.28
Table 3.29
Table 3.30
Table 3.31
Table 3.32
Table 3.33
Table 3.34
Table 3.35
Table 3.36
Table 3.37
Table 3.38
Table 3.39
Table 3.40
Section 4 Exception Handling
Table 4.1
Table 4.2
Table 4.3
Table 4.4
Table 4.5
Section 5 Memory Management Unit (MMU)
Table 5.1
Section 6 Cache
Table 6.1
Table 6.2
Table 6.3
Table 6.4
Table 6.5
Table 6.6
Rev. 1.00 Dec. 27, 2005 Page xxxviii of xlii
Examples of NOPX and NOPY Instruction Codes............................................... 116
Variation of ALU Fixed-Point Operations............................................................ 119
Correspondence between Operands and Registers ............................................... 119
Variation of ALU Integer Operations ................................................................... 124
Variation of ALU Logical Operations .................................................................. 125
Variation of Fixed-Point Multiply Operation ....................................................... 127
Correspondence between Operands and Registers ............................................... 127
Variation of Shift Operations................................................................................ 128
Operation Definition of PDMSB .......................................................................... 134
Variation of PDMSB Operation............................................................................ 135
Variation of Rounding Operation ......................................................................... 136
Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 137
Definition of Overflow Protection for Integer Arithmetic Operations.................. 137
Variation of Local Data Move Operations............................................................ 138
Correspondence between Operands and Registers ............................................... 139
DSP Mode Extended System Control Instructions ............................................... 140
Double Data Transfer Instruction ......................................................................... 142
Single Data Transfer Instructions ......................................................................... 143
Correspondence between DSP Data Transfer Operands and Registers ................ 144
DSP Operation Instructions .................................................................................. 145
Operation Code Map............................................................................................. 151
Exception Event Vectors ...................................................................................... 163
Instruction Positions and Restriction Types.......................................................... 173
SPC Value when Re-Execution Type Exception Occurs in Repeat Control
(RC[11:0] ≥ 2) ...................................................................................................... 176
Exception Acceptance in Repeat Loop ................................................................. 177
Instruction Where a Specific Exception Occurs when Memory Access
Exception Occurs in Repeat Control (SR.RC[11:0] ≥ 1) ...................................... 178
Access States Designated by D, C, and PR Bits ................................................... 199
LRU and Way Replacement (when Cache Locking Mechanism is Disabled)...... 216
Way Replacement when a PREF Instruction Misses the Cache ........................... 220
Way Replacement when Instructions other than the PREF Instruction
Miss the Cache...................................................................................................... 220
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)................ 220
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)................ 221
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)................ 221