HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 689

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.3.2
ECMR is a 32-bit readable/writable register and specifies the operating mode of the Ethernet
controller. The settings in this register are normally made in the initialization process following a
reset.
The operating mode setting must not be changed while the transmitting and receiving functions
are enabled. To switch the operating mode, return the EtherC and E-DMAC to their initial states
by means of the SWR bit in EDMR before making settings again.
Bit
31 to 14 
13
12
11
10
EtherC Mode Register (ECMR)
Bit Name
MCT
PRCEF


Initial
Value
All 0
0
0
0
0
R/W
R
R/W
R/W
R
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Multicast Address Frame Receive Mode
0: Frames other than the multicast address set by the
1: Only the multicast address set by the CAM entry
CRC Error Frame Reception Enable
0: A receive frame including a CRC error is received
1: A receive frame including a CRC error is received
When this bit is cleared to 0, the CRC error is
reflected in ECSR of the E-DMAC and the status of
the receive descriptor. When this bit is set to 1, a
frame is received as a normal frame.
Reserved
These bits are always read as 0. The write value
should always be 0.
CAM entry table 0 to 31 (H/L) registers are
received. However, if the on-chip CAM entry table
reference is disabled, all multicast address frames
are received.
table 0 to 31 (H/L) registers is received.
as a frame with an error.
as a frame without an error.
Rev. 1.00 Dec. 27, 2005 Page 645 of 932
Section 18 Ethernet Controller (EtherC)
REJ09B0269-0100