HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 221

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
Exception Retained in Repeat Control Period: In the repeat control period, an interrupt or some
exception will be retained to prevent an exception acceptance at an instruction where returning
from the exception cannot be performed correctly. For details, refer to repeat loop program
examples 1 to 4. In the examples, exceptions generated at instructions indicated as [B], [C], [C1],
or [C2], the following processing is executed.
• Interrupt, DMA address error
Note: * An interrupt request or a DMA address error exception request is retained in the
• User break before instruction execution
• User break after instruction execution
Table 4.4
Exception Type
Interrupt
DMA address error
User break before instruction execution
User break after instruction execution
An exception request is not accepted and retained at instructions [B] and [C]. If an instruction
indicates as [A] is executed at the next time, an exception request is accepted.* As shown in
program examples 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat
loop consisting of four instructions or less.
A user break before instruction execution is accepted at instruction [B], and an address of
instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but
the exception request is retained until an instruction [A] or [B] is executed at the next time.
Then, the exception request is accepted before an instruction [A] or [B] is executed. In this
case, an address of instruction [A] or [B] is saved in the SPC.
A user break after instruction execution cannot be accepted at instructions [B] and [C] but the
exception request is retained until an instruction [A] or [B] is executed at the next time. Then,
the exception request is accepted before an instruction [A] or [B] is executed. In this case, an
address of instruction [A] or [B] is saved in the SPC.
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction.
interrupt controller (INTC) and the direct memory access controller (DMAC) until the
CPU can accept a request.
Exception Acceptance in Repeat Loop
Not accepted
Accepted
Not accepted
Instruction [B]
Not accepted
Rev. 1.00 Dec. 27, 2005 Page 177 of 932
Section 4 Exception Handling
Instruction [C]
Not accepted
Not accepted
Not accepted
Not accepted
REJ09B0269-0100