HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 512

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 468 of 932
REJ09B0269-0100
Bit
4
3
2
1
Bit Name
TS1
TS0
IE
TE
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/(W)* Transfer End Flag
Description
Transfer Size
Specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word (two bytes) size
10: Longword (four bytes) size
11: 16-byte (four longwords) size
Interrupt Enable
Specifies whether or not an interrupt request is generated
to the CPU at the end of the DMA transfer. Setting this bit
to 1 generates an interrupt request (DEI) to the CPU
when the TE bit is set to 1.
0: Interrupt request is disabled
1: Interrupt request is enabled
The TE bit is set to 1 when data transfer ends when
DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
•
•
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
1: DMA transfer ends by the specified count (DMATCR =
[Clearing condition]
Writing 0 after reading 1 from this bit
interrupted
0)
DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR becomes 0.
DMA transfer is ended by clearing the DE bit and
DME bit in the DMA operation register (DMAOR).