HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 348

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Power-Down Modes
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT’s timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT’s timer counter (WTCNT) to 0 and the CKS2 to CKS0 bits in WTCSR to
3. After the STBY bit in STBCR is set to 1, a SLEEP instruction is executed.
4. Software standby mode is entered and the clocks within the chip are halted. The STATUS1
Canceling Software Standby Mode: Software standby mode is canceled by an interrupt (NMI,
IRQ, IRL, or RTC) or a reset.
• Canceling with an Interrupt
The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRQ*
RTC*
after the time set in the WDT’s timer control/status register has elapsed. The STATUS1 and
STATUS0 pins go low. Interrupt exception handling then begins and a code indicating the
interrupt source is set in INTEVT and INTEVT2. After the branch to the interrupt handling
routine, clear the STBY bit in STBCR. The WDT stops automatically. If the STBY bit is not
cleared, the WDT continues operation and a transition is made to software standby mode*
WTCNT reaches H'80. A manual reset is not accepted until the STBY bit is cleared to 0.
Interrupts are accepted in software standby mode even when the BL bit in SR is 1. If necessary,
save SPC and SSR to the stack before executing the SLEEP instruction.
Immediately after an interrupt is detected, the phase of the CKIO pin clock output may be
unstable, until the software standby mode is canceled.
Notes: 1. Only when the RTC is used, software standby mode can be canceled by an IRQ, IRL,
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appropriate values to secure the specified oscillation settling time.
and STATUS0 pins output low and high, respectively.
1
interrupt, the clock will be supplied to the entire chip and software standby mode canceled
2. This standby mode can be canceled only by a power-on reset.
or RTC.
1
, IRL*
1
2
, or
when