HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 15

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

3.3
3.4
3.5
3.6
Section 4 Exception Handling ...........................................................................155
4.1
4.2
3.2.4
CPU Extended Instructions.................................................................................................. 78
3.3.1
3.3.2
DSP Data Transfer Instructions ........................................................................................... 93
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
DSP Data Operation Instructions ....................................................................................... 106
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.5.6
3.5.7
3.5.8
3.5.9
3.5.10 Rounding Operation.............................................................................................. 135
3.5.11 Overflow Protection.............................................................................................. 137
3.5.12 Local Data Move Instruction ................................................................................ 138
3.5.13 Operand Conflict................................................................................................... 139
DSP Extended Function Instruction Set............................................................................. 140
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
Register Descriptions ......................................................................................................... 155
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
Exception Handling Function ............................................................................................ 159
4.2.1
DSP Registers ......................................................................................................... 77
Repeat Control Instructions .................................................................................... 78
Extended Repeat Control Instructions .................................................................... 88
General Registers.................................................................................................... 97
DSP Data Addressing ............................................................................................. 99
Modulo Addressing............................................................................................... 100
Memory Data Formats .......................................................................................... 103
Instruction Formats of Double and Single Transfer Instructions .......................... 103
DSP Registers ....................................................................................................... 106
DSP Operation Instruction Set.............................................................................. 111
DSP-Type Data Formats ....................................................................................... 116
ALU Fixed-Point Operations................................................................................ 118
ALU Integer Operations ....................................................................................... 123
ALU Logical Operations....................................................................................... 125
Fixed-Point Multiply Operation............................................................................ 126
Shift Operations .................................................................................................... 128
Most Significant Bit Detection Operation............................................................. 132
CPU Extended Instructions................................................................................... 140
Double-Data Transfer Instructions........................................................................ 142
Single-Data Transfer Instructions ......................................................................... 143
DSP Operation Instructions .................................................................................. 145
Operation Code Map in DSP Mode ...................................................................... 151
TRAPA Exception Register (TRA) ...................................................................... 156
Exception Event Register (EXPEVT)................................................................... 157
Interrupt Event Register (INTEVT)...................................................................... 157
Interrupt Event Register 2 (INTEVT2)................................................................. 158
Exception Address Register (TEA)....................................................................... 158
Exception Handling Flow ..................................................................................... 159
Rev. 1.00 Dec. 27, 2005 Page xiii of xlii