HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 16

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.3
4.4
4.5
Section 5 Memory Management Unit (MMU).................................................. 181
5.1
5.2
5.3
5.4
5.5
5.6
Rev. 1.00 Dec. 27, 2005 Page xiv of xlii
4.2.2
4.2.3
4.2.4
4.2.5
Individual Exception Operations ....................................................................................... 165
4.3.1
4.3.2
4.3.3
Exception Processing while DSP Extension Function is Valid ......................................... 172
4.4.1
4.4.2
4.4.3
Usage Notes ....................................................................................................................... 179
Role of MMU .................................................................................................................... 181
5.1.1
Register Descriptions......................................................................................................... 189
5.2.1
5.2.2
5.2.3
5.2.4
TLB Functions ................................................................................................................... 193
5.3.1
5.3.2
5.3.3
5.3.4
MMU Functions................................................................................................................. 200
5.4.1
5.4.2
5.4.3
5.4.4
MMU Exceptions............................................................................................................... 205
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Memory-Mapped TLB....................................................................................................... 211
5.6.1
Exception Vector Addresses................................................................................. 160
Exception Codes ................................................................................................... 160
Exception Request and BL Bit (Multiple Exception Prevention) ......................... 160
Exception Source Acceptance Timing and Priority .............................................. 161
Resets.................................................................................................................... 165
General Exceptions............................................................................................... 166
General Exceptions (MMU Exceptions)............................................................... 169
Illegal Instruction Exception and Slot Illegal Instruction Exception .................... 172
CPU Address Error ............................................................................................... 172
Exception in Repeat Control Period ..................................................................... 172
MMU of This LSI................................................................................................. 183
Page Table Entry Register High (PTEH).............................................................. 190
Page Table Entry Register Low (PTEL) ............................................................... 191
Translation Table Base Register (TTB) ................................................................ 191
MMU Control Register (MMUCR) ...................................................................... 191
Configuration of the TLB ..................................................................................... 193
TLB Indexing........................................................................................................ 195
TLB Address Comparison .................................................................................... 196
Page Management Information............................................................................. 198
MMU Hardware Management.............................................................................. 200
MMU Software Management ............................................................................... 200
MMU Instruction (LDTLB).................................................................................. 201
Avoiding Synonym Problems............................................................................... 202
TLB Miss Exception............................................................................................. 205
TLB Protection Violation Exception .................................................................... 206
TLB Invalid Exception ......................................................................................... 207
Initial Page Write Exception................................................................................. 208
MMU Exception in Repeat Loop.......................................................................... 209
Address Array....................................................................................................... 211