HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 217

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 4.2
Notes: 1. A specific address is specified in the SPC if an exception occurs while SR.RC[11:0] ≥2.
• Example 1: Repeat loop consisting of four or greater instructions
Instruction
Position
[A]
[B]
[C1]
[C2]
RptStart: instr1
RptDtct:
RptEnd:
2. There are a greater number of instructions that can be illegal instructions while
3. An interrupt, break or DMA address error request is retained while SR.RC[11:0] ≥1.
4. A specific exception code is specified while SR.RC[11:0] ≥1.
SR.RC[11:0] ≥1.
Instruction Positions and Restriction Types
LDRS RptStart
LDRS RptDtct + 4
SETRC #4
instr0
………
………
RptDtct
RptDtct1
RptDtct2
RptDtct3
InstrNext
SPC*
Illegal
1
; [A]
Illegal
Instruction*
Added
Added
; [A]
; [A]
; [A]
; [A][Repeat start instruction]
; [A]
; [A]
; [B] A repeat detection
; [C1]
; [C2]
; [C2][Repeat end instruction]
; [A]
2
instruction is an
instruction three
instructions before a
repeat end instruction
Interrupt,
Break*
Retained
Retained
Retained
Rev. 1.00 Dec. 27, 2005 Page 173 of 932
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Section 4 Exception Handling
CPU Address
Error*
Instruction/data
Instruction/data
REJ09B0269-0100
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