HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 780

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Rev. 1.00 Dec. 27, 2005 Page 736 of 932
REJ09B0269-0100
Bit
23
22
21
Bit Name
ADE
ECI
TC
Initial
Value
0
0
0
R/W
R/W
R
R/W
Description
Address Error
Indicates that the memory address that the E-DMAC
tried to transfer is found illegal.
0: Illegal memory address not detected (normal
1: Illegal memory address detected
Note: When an address error is detected, the
EtherC Status Register Interrupt Source
This bit is a read-only bit. When the source of an
ECSR interrupt in the EtherC is cleared, this bit is
also cleared.
0: EtherC status interrupt source has not been
1: EtherC status interrupt source has been detected
Frame Transmit Complete
Indicates that all the data specified by the transmit
descriptor has been transmitted from the EtherC. This
bit is set to 1, assuming the completion of
transmission, when transmission of one frame is
completed in single-frame/single-descriptor operation
or when the last data of a frame has been transmitted
and the transmit descriptor valid bit (TACT) of the
next descriptor is not set in for the processing of
multi-buffer frame based on single-frame/multi-
descriptor operation. After frame transmission, the E-
DMAC writes the transmission status back to the
relevant descriptor.
0: Transfer not complete, or no transfer directive
1: Transfer complete
operation)
detected
E-DMAC halts transmitting/receiving. To
resume the operation, execute a software
reset with the SWR bit in EDMR.