HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 134

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
• Example 3: Repeat loop consisting of two instructions
• Example 4: Repeat loop consisting of one instructions
In extended repeat control instructions, a repeat start instruction address and a repeat end
instruction address are stored in the RS register and RE register, respectively, regardless of the
number of repeat instructions. In addition, the extended repeat control can be performed by using
the LDRC instruction instead of the SETRC instruction. During the extended repeat control, a
repeat loop can be recognized by executing a repeat end instruction. Therefore, there is no
restriction on branches or exceptions.
Extended Repeat Control Instructions: To describe the extended repeat loop, the repeat start
and end addresses must be specified to the RS and RE registers by the LDRS and LDRE
instructions, respectively. For the LDRS and LDRE instructions of the extended repeat control
instructions, the LDRS and LDRE instructions of the compatible repeat control instructions are
used. The number of repetitions are specified by the LDRC instruction. An 8-bit immediate data or
the general register values can be used as an operand of the LDRC instruction. If 256 or greater
value is specified to the RC, use the LDRC Rm type instructions.
Rev. 1.00 Dec. 27, 2005 Page 90 of 1044
REJ09B0269-0100
RptStart: instr1
RptEnd:
Rptstart:
RptEnd:
LDRS RptStart
LDRE RptEnd
LDRC #4
instr0
instr2
LDRS RptStart
LDRE RptEnd
LDRC #4
instr0
instr1
; Sets repeat start instruction address
; Sets repeat end instruction address
; Sets the number of repetitions (4) to
; At least one instruction is required
; [Repeat start instruction]
; [Repeat end instruction]
; Sets repeat start instruction address
; Sets repeat end instruction address
; Sets the number of repetitions (4) to
; At least one instruction is required
; [Repeat start instruction]=
to the RS register
to the RE register
the RC[11:0] bits of the SR register
from LDRC instruction to [Repeat start
instruction]
to the RS register
to the RE register
the RC[11:0] bits of the SR register
from LDRC instruction to [Repeat start
instruction] RptStart:
[Repeat end instruction]