HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 683

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.2
Table 18.1 lists the pin configuration of the EtherC.
Table 18.1 Pin Configuration
Name
Transmit clock
Receive clock
Transmit enable
Transmit data
Transmit error
Receive data valid
Receive data
Receive error
Carrier detection
Collision detection
Management data
clock
Management data
I/O
Link status
General-purpose
external output
Wake-On-LAN
Transmit clock
Receive clock
Input/Output Pins
Port
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Abbreviation I/O
TX-CLK0*
RX-CLK0*
TX-EN0*
ETXD03 to
ETXD00*
TX-ER0*
RX-DV0*
ERXD03 to
ERXD00*
RX-ER0*
CRS0*
COL0*
MDC0*
MDIO0*
LNKSTA0
EXOUT0
WOL0
TX-CLK1*
RX-CLK1*
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
I
O
O
O
I
I
I
I
I
O
I/O
I
O
O
I
I
Function
TX-EN, ETXD3 to ETXD0, TX-ER timing
reference signal
RX-DV, ERXD3 to ERXD0, RX-ER timing
reference signal
Indicates that transmit data is ready on
ETXD3 to ETXD0
4-bit transmit data
Notifies PHY_LSI of error during
transmission
Indicates that valid receive data is on
ERXD3 to ERXD0
4-bit receive data
Identifies error state occurred during data
reception
Carrier detection signal
Collision detection signal
Reference clock signal for information
transfer via MDIO
Bidirectional signal for exchange of
management information between this LSI
and PHY
Inputs link status from PHY
Signal indicating value of register-bit
(ECMR0-ELB)
Signal indicating reception of Magic Packet
TX-EN, ETXD3 to ETXD0, TX-ER timing
reference signal
RX-DV, ERXD3 to ERXD0, RX-ER timing
reference signal
Rev. 1.00 Dec. 27, 2005 Page 639 of 932
Section 18 Ethernet Controller (EtherC)
REJ09B0269-0100