HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 460

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Bus State Controller (BSC)
where the READA command is output to the Td1 cycle where the read data is latched can be
specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in
CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number
of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency
for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency
in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a
latch circuit between this LSI and the synchronous DRAM.
Rev. 1.00 Dec. 27, 2005 Page 416 of 932
REJ09B0269-0100
A12/A11*
A25 to A0
D31 to D0
DACKn*
Notes:
DQMxx
RD/WR
CKIO
RAS
CAS
CSn
BS
1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
2
1
Figure 12.14 Burst Read Basic Timing (Auto Precharge)
Tr
Tc1
Tc2
Td1
Td2
Tc3
Td3
Tc4
Td4
Tde
Tap