HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 775

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.2.2
EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC. After
writing 1 to the TR bit in this register, the E-DMAC reads the transmit descriptor at the address
specified by TDLAR. If the TACT bit of this descriptor is set to 1 (valid), transmit DMA transfer
by the E-DMAC starts. When DMA transfer based on the first transmit descriptor is completed,
the E-DMAC reads the next transmit descriptor. If the TACT bit of that descriptor is set to 1
(valid), the E-DMAC continues transmit DMA operation. If the TACT bit of a transmit descriptor
is cleared to 0 (invalid), the E-DMAC clears the TR bit and stops transmit DMAC operation.
For details of writing to the TR bit, see section 19.4.1, Using of EDTRR and EDRRR.
Bit
0
E-DMAC Transmit Request Register (EDTRR)
Bit Name
SWR
Initial
Value
0
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
R/W
R/W
Description
Software Reset
By writing 1 to this bit, the registers of the E-DMAC
other than TDLAR, RDLAR, and RMFCR and the
registers of EtherC other than TSU-related registers
can be initialized. (The registers whose names start
with TSU_ are not initialized.) The SWR bit in EDMR0
initializes the EDMAC0 and MAC-0 registers in the
EtherC. The SWR bit in EDMR1 initializes EDMAC1
and MAC-1 registers in the EtherC. When transfer
operation is enabled by specifying the relay enable
register (Port 0 to 1) (TSU_FWEN0) and the relay
enable register (Port 1 to 0) (TSU_FWEN1) in the
EtherC, software reset should not be performed by
using this bit. While a software reset is issued (64
cycles of the internal bus clock Bφ), accesses to the
all Ethernet-related registers are prohibited.
Software reset period (example):
When Bφ = 100 MHz: 0.64 µS
When Bφ = 66 MHz: 0.97 µS
When Bφ = 50 MHz: 1.28 µS
When Bφ = 33 MHz: 1.94 µS
This bit is always read as 0.
1: EtherC and E-DMAC are reset (when writing)
Rev. 1.00 Dec. 27, 2005 Page 731 of 932
REJ09B0269-0100