HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 119

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Note: When data is written to the SR register, 0 should be written to bits that are specified as 0.
Repeat Start Register (RS): The repeat start register (RS) holds the start address of a loop repeat
module that is controlled by the repeat function. This register can be accessed in DSP mode. At
reset, the initial value of this register is undefined. This register is not affected in the exception
handling state.
Repeat End Register (RE): The repeat end register (RE) holds the end address of a loop repeat
module that is controlled by the repeat function. This register can be accessed in DSP mode. At
reset, this register is initialized to 0. This register is not affected in the exception handling state.
Modulo Register (MOD): The modulo register stores the modulo end address and modulo start
address for modulo addressing in upper and lower 16 bits. The upper and lower 16 bits of the
modulo register are referred to as the ME register and MS register, respectively. This register can
be accessed in DSP mode. At reset, the initial value of this register is undefined. This register is
not affected in the exception handling state.
The above registers can be accessed by the control register load instruction (LDC) and store
instruction (STC). Note that the LDC and STC instructions for the RS, RE, and MOD registers can
be used only in privileged DSP mode and user DSP mode. The LDC and STC instruction for the
SR register can be executed only when the MD bit is set to 1 or in user DSP mode. Note, however,
that the LDC and STC instructions can modify only the RC11 to RC0, RF1 to RF0, DMX, and
DMY bits in the SR, as described below.
• In user mode, if the LCD and STC instructions are used for the RS, an illegal instruction
Bit
11
10
9 to 4
3
2
1 to 0
exception occurs.
Bit Name
DMY
DMX

FR1
FR0

Initial
Value
0
0

0
0

R/W
R/W
R/W

R/W
R/W

Description
Modulo Control Bits
Enable or disable modulo addressing for X/Y memory
access. These bits can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, these
bits are initialized to 0. These bits are not affected in the
exception handling state.
For details, refer to section 2, CPU.
Repeat Flag Bits
Used by repeat control instructions. These bits can be
modified in privileged mode, privileged DSP mode, or user
DSP mode. At reset, these bits are initialized to 0. These
bits are not affected in the exception handling state.
For details, refer to section 2, CPU.
Rev. 1.00 Dec. 27, 2005 Page 75 of 1044
Section 3 DSP Operating Unit
REJ09B0269-0100