HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 128

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 3 DSP Operating Unit
• Example 7: Repeat loop consisting of two instructions (extended to the instruction stream
• Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction
In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE
registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC
and STC instructions for the SR register. These instructions should be used if an exception is
enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS
and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception
handling and by restoring the stored values after exception handling. However, note that there are
some restrictions on exception acceptance during repeat loop execution. For details refer to
Restrictions on Repeat Loop Control in section 3.3.1, Repeat Control Instructions and section 4,
Exception Handling.
Table 3.6
Rev. 1.00 Dec. 27, 2005 Page 84 of 1044
REJ09B0269-0100
Instruction
STC RS, Rn
STC RE, Rn
STC.L RS, @-Rn
STC.L RE, @-Rn
LDC.L @Rn+, RS
LDC.L @Rn+, RE
LDC Rn,RS
LDC Rn, RE
RptStart: instr1
RptEnd:
RptStart:
RptEnd:
shown in example 3, above)
stream shown in example 4, above)
DSP Mode Extended System Control Instructions
REPEAT RptStart, RptEnd, #4
instr0
instr2
REPEAT RptStart, RptEnd, #4
instr0
instr1
Operation
RS→Rn
RE→Rn
Rn-4→Rn, RS→(Rn)
Rn-4→Rn, RE→(Rn)
(Rn)→RS, Rn+4→Rn
(Rn)→RE, Rn+4→Rn
Rn →RS
Rn→RE
;
; [Repeat start instruction]
; [Repeat end instruction]
;
; [Repeat start instruction] ==
[Repeat end instruction]
Number of
Execution States
1
1
1
1
4
4
4
4

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