HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 508

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Direct Memory Access Controller (DMAC)
13.3.3
DMATCR is a 32-bit readable/writable registers that specifies the DMA transfer count. The
number of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, DMATCR indicates
the remaining transfer count.
The upper eight bits of DMATCR will return 0 if read, and should only be written with 0.
To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one.
DMATCR is undefined at reset and retains the current value in standby or module standby mode.
13.3.4
CHCR is a 32-bit readable/writable register that controls the DMA transfer mode.
CHCR is initialized to H'00000000 at reset and retains the current value in the standby or module
standby mode.
Rev. 1.00 Dec. 27, 2005 Page 464 of 932
REJ09B0269-0100
Bit
31 to
24
23
Bit Name

DO
DMA Transfer Count Register (DMATCR)
DMA Channel Control Register (CHCR)
Initial
Value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
DMA Overrun
Selects whether the DREQ is detected by overrun 0 or by
overrun 1.
This bit is valid only in CHCR0 and CHCR1.This bit is
reserved and always read as 0 in CHCR2 to CHCR5. The
write value should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1