HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 626

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
16.5
SCIF Interrupt Sources and DMAC
The SCIF supports four interrupt sources—transmit-FIFO-data-empty interrupt (TXI), receive-
error interrupt (ERI), receive-FIFO-data-full interrupt (RXI), and break interrupt (BRI). Table 16.6
shows the interrupt sources and their order of priority. For priorities and the relationship with non-
the SCIF interrupts, see section 4, Exception Handling. The interrupt sources can be enabled or
disabled by means of the TIE, RIE, and REIE bits in SCSCR. A separate interrupt request is sent
to the interrupt controller for each of these interrupt sources.
When the TXI is enabled by the TIE bit, if the TDFE flag in SCFSR is set to 1, a TXI request and
a transmit-FIFO-data-empty DMA transfer request are generated. When the TXI is disabled by the
TIE bit, if the TDFE flag is set to 1, only the transmit-FIFO-data-empty DMA transfer request is
generated. The DMAC can be activated and data transfer performed on generation of the transmit-
FIFO-data-empty DMA transfer request.
When the RXI is enabled by the RIE bit, if the RDF flag or DR flag in SCFSR is set to 1, an RXI
request and a receive-FIFO-data-full DMA transfer request are generated. When the RXI is
disabled by the RIE bit, if the RDF flag or DR flag is set to 1, only the receive-FIFO-data-full
DMA transfer request is generated. The DMAC can be activated and data transfer performed on
generation of the receive-FIFO-data-full DMA transfer request. The generation of the RXI and the
receive-FIFO-data-full DMA transfer requests by setting the DR flag to 1 occurs only in
asynchronous mode.
When the BRK flag in SCFSR or the ORER flag in SCLSR is set to 1, a BRI request is generated.
When using the DMAC for transmission/reception, set and enable the DMAC before making the
SCIF settings. See section 13, Direct Memory Access Controller (DMAC), for details on the
DMAC setting procedure. Also set the RXI and TXI requests not to be output to the interrupt
controller. If the interrupt requests are set to be generated, the interrupt requests to the interrupt
controller are cleared by the DMAC regardless of the interrupt handling program.
When the RIE bit is cleared to 0 and the REIE bit is set to 1 in SCSCR, the ERI or BRI request
can be generated without generating the RXI request. Note that the TXI indicates that writing the
transmit data is enabled, while the RXI indicates that the receive data is in SCFRDR.
Rev. 1.00 Dec. 27, 2005 Page 582 of 932
REJ09B0269-0100