HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 124

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 3 DSP Operating Unit
• Example 2: Repeat loop consisting of three instructions
• Example 3: Repeat loop consisting of two instructions
Rev. 1.00 Dec. 27, 2005 Page 80 of 1044
REJ09B0269-0100
RptDtct:
RptStart: instr1
RptEnd:
RptDtct:
RptStart: instr1
RptEnd:
LDRS RptStart +4
LDRE RptStart +4
SETRC #4
instr0
Instr2
instr3
LDRS RptStart +6
LDRE RptStart +4
SETRC #4
instr0
instr2
; Sets (repeat detection instruction
; Sets (repeat detection instruction
; Sets the number of repetitions (4) to
; If RE-RS==0 during SETRC instruction
; An instruction prior to the Repeat
; [Repeat start instruction]
;
; [Repeat end instruction]
; Sets (repeat detection instruction
; Sets (repeat detection instruction
; Sets the number of repetitions (4) to
; If RE-RS==-2 during SETRC instruction
; An instruction prior to the Repeat
; [Repeat start instruction]
; [Repeat end instruction]
address + 4) to the RS register
address + 4) to the RE register
the RC[11:0] bits of the SR register
execution, the repeat loop is regarded
as three-instruction repeat.
start instruction is regarded as a
repeat detection instruction.
address + 6) to the RS register
address + 4) to the RE register
the RC[11:0] bits of the SR register
execution, the repeat loop is regarded
as two-instruction repeat.
start instruction is regarded as a
repeat detection instruction.

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