HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 612

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 16 Serial Communication Interface with FIFO (SCIF)
Serial Data Reception: Figures 16.6 and 16.7 show a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCIF for reception.
Rev. 1.00 Dec. 27, 2005 Page 568 of 932
REJ09B0269-0100
No
No
SCFSR and ORER flag in SCLSR
Read ER, DR, and BRK flags in
SCFRDR, and clear RDF flag
Clear RE bit in SCSCR to 0
Read RDF flag in SCFSR
Read receive data from
All data received?
Start of reception
End of reception
in SCFSR to 0
ER, DR, BRK,
or ORER = 1?
RDF = 1?
Figure 16.6 Sample Serial Reception Flowchart (1)
No
Yes
Yes
Error handling
Yes
1. Receive error handling and break detection:
2. SCIF status check and receive data read:
3. Serial reception continuation procedure:
Read the DR, ER, and BRK flags in SCFSR
and ORER flag in SCLSR to identify any
error, perform the appropriate error
handling, then clear the DR, ER, BRK, and
ORER flags to 0. In the case of a framing
error, a break can also be detected by
reading the value of the RxD pin.
Read SCFSR and check that RDF = 1, then
read the receive data in SCFRDR, read 1
from the RDF flag, and then clear the RDF
flag to 0. The transition of the RDF flag
from 0 to 1 can also be identified by an RXI
interrupt.
To continue serial reception, read at least
the receive trigger set number of data bytes
from SCFRDR, read 1 from the RDF flag,
and then clear the RDF flag to 0. The
number of receive data bytes in SCFRDR
can be ascertained by reading the lower
bits of SCFDR.

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