HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 225

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 5 Memory Management Unit (MMU)
Section 5 Memory Management Unit (MMU)
This LSI has an on-chip memory management unit (MMU) that supports a virtual memory system.
The on-chip translation look-aside buffer (TLB) caches information for user-created address
translation tables located in external memory. It enables high-speed translation of virtual addresses
into physical addresses. Address translation uses the paging system and supports two page sizes (1
kbyte or 4 kbytes). The access rights to virtual address space can be set for each of the privileged
and user modes to provide memory protection.
5.1
Role of MMU
The MMU is a feature designed to make efficient use of physical memory. As shown in figure 5.1,
if a process is smaller in size than the physical memory, the entire process can be mapped onto
physical memory. However, if the process increases in size to the extent that it no longer fits into
physical memory, it becomes necessary to partition the process and to map those parts requiring
execution onto memory as occasion demands (figure 5.1 (1)). Having the process itself consider
this mapping onto physical memory would impose a large burden on the process. To lighten this
burden, the idea of virtual memory was born as a means of performing en bloc mapping onto
physical memory (figure 5.1 (2)). In a virtual memory system, substantially more virtual memory
than physical memory is provided, and the process is mapped onto this virtual memory. Thus a
process only has to consider operation in virtual memory. Mapping from virtual memory to
physical memory is handled by the MMU. The MMU is normally controlled by the operating
system, switching physical memory to allow the virtual memory required by a process to be
mapped onto physical memory in a smooth fashion. Switching of physical memory is performed
via secondary storage, etc.
The virtual memory system that came into being in this way is particularly effective in a time-
sharing system (TSS) in which a number of processes are running simultaneously (figure 5.1 (3)).
If processes running in a TSS had to take mapping onto virtual memory into consideration while
running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this
load on the individual processes and so improve efficiency (figure 5.1 (4)). In the virtual memory
system, virtual memory is allocated to each process. The task of the MMU is to perform efficient
mapping of these virtual memory areas onto physical memory. It also has a memory protection
feature that prevents one process from inadvertently accessing another process’s physical memory.
When address translation from virtual memory to physical memory is performed using the MMU,
it may occur that the relevant translation information is not recorded in the MMU, with the result
that one process may inadvertently access the virtual memory allocated to another process. In this
case, the MMU will generate an exception, change the physical memory mapping, and record the
new address translation information.
Rev. 1.00 Dec. 27, 2005 Page 181 of 932
REJ09B0269-0100