HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 372

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 On-Chip Oscillation Circuits
11.8.2
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
3. When the frequency control register (FRQCR) is written, the processor stop temporarily. The
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
5. The counter stops at the values H'00.
6. Before changing the WTCNT after the execution of the frequency change instruction, always
11.8.3
1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
11.8.4
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
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is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
the counter in WTCNT. These values should ensure that the time till count overflow is longer
than the clock oscillation settling time.
WDT starts counting.
resumes operation. The WOVF flag in WTCSR is not set at this time.
confirm that the value of the WTCNT is H'00 by reading the WTCNT.
clock in the CKS2 to CKS0 bits, and set the initial value of the counter in WTCNT.
the counter from overflowing.
type of reset specified by the RSTS bit. The counter then resumes counting.
set the initial value of the counter in WTCNT.
timer interrupt request is sent to INTC. The counter then resumes counting.
Changing Frequency
Using Watchdog Timer Mode
Using Interval Timer Mode