HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 158

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
Table 3.19 DC Bit Update Definitions
Rev. 1.00 Dec. 27, 2005 Page 114 of 1044
REJ09B0269-0100
0
0
0
0
1
1
1
1
CS [2:0] Condition Mode
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Carry or borrow
mode
Negative value
mode
Zero value mode
Overflow mode
Signed greater-than
mode
Signed greater-or-
equal mode
Reserved (setting prohibited)
Reserved (setting prohibited)
Description
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
When a PSHA or PSHL shift instruction is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
When an ALU or shift (PSHA) arithmetic operation is executed,
the MSB of the result, including the guard bits, is copied into the
DC bit.
When an ALU or shift (PSHL) logical operation is executed, the
MSB of the result, excluding the guard bits, is copied into the DC
bit.
The DC bit is set if the result of an ALU or shift operation is all-
zeros, and is cleared otherwise.
The DC bit is set if the result of an ALU or shift (PSHA) arithmetic
operation exceeds the destination register range, excluding the
guard bits, and is cleared otherwise.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
This mode is similar to signed greater-or-equal mode, but DC is
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
DC = 0; In case of logical operation
If the result of an ALU or shift (PSHA) arithmetic operation
exceeds the destination register range, including the guard bits
(over-range), the definition is the same as in negative value
mode. If the result is not over-range, the definition is the opposite
of that in negative value mode.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
DC = ~(negative value ^ over-range);
DC = 0 ; In case of logical operation
In case of arithmetic operation
In case of arithmetic operation