HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 87

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The little endian mode can also be specified as data format. Either big-endian or little-endian
mode can be selected according to the external pin (MD5) at a power-on reset. When MD5 is low
at reset, the processor operates in big-endian mode. When MD5 is high at reset, the processor
operates in little-endian mode. The endian mode cannot be modified dynamically.
In little endian mode, the MSB byte in the register corresponds to the highest address in the
memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For
example, if the contents of the general register R0 is stored at an address indicated by the general
register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the (R1+3)
and the LSB byte of the R1 register is stored at the address indicated by the R1.
If the little endian mode is selected, the on-chip memory are accessed in little endian mode.
However, the on-chip device registers assigned to memory are accessed in big endian mode. Note
that the available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode,
Byte position
Byte position
Byte position
Byte position
in memory
in memory
in R0
in R0
the instruction code must be stored from lower byte to upper byte in this order from the
word boundary of the memory.
31
31
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
@(R1+0) @(R1+1) @(R1+2) @(R1+3)
[7:0]
23
Example: MOV.B R0, @R1
23
Example: MOV.B R0, @R1
Figure 2.8 Data Format on Memory (Little Endian Mode)
(a) Byte access
Figure 2.7 Data Format on Memory (Big Endian Mode)
(a) Byte access
(R1 = Address 4n)
(R1 = Address 4n)
15
15
7
7
[7:0]
[7:0]
[7:0]
0
0
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
@(R1+0) @(R1+1) @(R1+2) @(R1+3)
[15:8]
Example: MOV.W R0, @R1
Example: MOV.W R0, @R1
(b) Word access
(b) Word access
[7:0]
(R1 = Address 4n)
(R1 = Address 4n)
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
Rev. 1.00 Dec. 27, 2005 Page 43 of 932
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
@(R1+0) @(R1+1) @(R1+2) @(R1+3)
[31:24]
[31:24]
[31:24]
[31:24]
Example: MOV.L R0, @R1
(c) Longword access
Example: MOV.L R0, @R1
(c) Longword access
(R1 = Address 4n)
[23:16]
[23:16]
[23:16]
[23:16]
(R1 = Address 4n)
REJ09B0269-0100
Section 2 CPU
[15:8]
[15:8]
[15:8]
[15:8]
[7:0]
[7:0]
[7:0]
[7:0]