HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 646

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
Rev. 1.00 Dec. 27, 2005 Page 602 of 932
REJ09B0269-0100
Bit
7
6
5
4
3
2
1
0
Bit Name
RFWM2
RFWM1
RFWM0
RFUA4
RFUA3
RFUA2
RFUA1
RFUA0
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
Description
Receive FIFO Watermark
A transfer request to the receive FIFO is issued by the RDREQ
bit in SISTR. The receive FIFO is always used as 16 stages of
FIFO regardless of these bit settings.
000: Issue a transfer request when 1 stage or more of receive
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: Reserved (setting prohibited)
100: Issue a transfer request when 4 or more stages of receive
101: Issue a transfer request when 8 or more stages of receive
110: Issue a transfer request when 12 or more stages of
111: Issue a transfer request when 16 stages of receive FIFO
Receive FIFO Usable Area
Indicate the number of words that can be transferred by the
CPU or DMAC as B′00000 to B′10000.
FIFO are valid.
FIFO are valid.
FIFO are valid.
receive FIFO are valid.
are valid.