HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 122

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
3.3
3.3.1
In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this
function, loop programs can be executed without overhead caused by the compare and branch
instructions.
Examples of Repeat Loop Programs: Examples of repeat loop programs are shown below.
• Example 1: Repeat loop consisting of 4 or more instructions
In the above program example, instructions from the RptStart address (instr1 instruction) to the
RptEnd address (instrN instruction) are repeated four times. These repeated instructions in the
program are called repeat loop. The start and end instructions of the repeat loop are called the
repeat start instruction and repeat end instruction, respectively. The CPU sequentially executes
instructions and starts repeat loop control if the CPU detects the completion of a specific
instruction. This specific instruction is called the repeat detection instruction. In a repeat loop
consisting of 4 or more instructions, an instruction three instructions prior to the repeat end
instruction is regarded as the repeat detection instruction. In a repeat loop consisting of 4 or more
instructions, the same instruction is regarded as the RptStart instruction and RptDtct instruction.
Rev. 1.00 Dec. 27, 2005 Page 78 of 1044
REJ09B0269-0100
RptStart: instr1
RptDtct:
RptEnd2:
RptEnd1:
RptEnd:
CPU Extended Instructions
Repeat Control Instructions
LDRS RptStart
LDRE RptStart +4
SETRC #4
Instr0
... ...
... ...
instr(N-3)
instr(N-2)
instr(N-1)
instrN
; Sets repeat start instruction address
; Sets (repeat detection instruction
; Sets the number of repetitions (4) to
; At least one instruction is required
; [Repeat start instruction]
;
;
; Three instruction prior to the repeat
;
;
; [Repeat end instruction]
to the RS register
address + 4) to the RE register
the RC[11:0] bits of the SR register
from SETRC instruction to [Repeat start
instruction]
end instruction is regarded as repeat
detection instruction