HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 831

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

21.1
This LSI has three 8-bit ports (ports A to C). All port pins are multiplexed with other pin functions
(the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control).
Each port has a data register which stores data for the pins.
21.2
21.2.1
PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT
to PA0DT correspond to pins PTA7 to PTA0. PADR is initialized to H′00 by a power-on reset but
is not initialized by a manual reset, in standby mode, or sleep mode.
Bit
7
6
5
4
3
2
1
0
Bit Name
PA7DT
PA6DT
PA5DT
PA4DT
PA3DT
PA2DT
PA1DT
PA0DT
Overview
Register Descriptions
Port A Data Register (PADR)
Initial
Value
0
0
0
0
0
0
0
0
Section 21 I/O Ports
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
When the pin function is general output port, if the port
is read, the value of the corresponding PADR bit is
returned directly. When the function is general input
port, if the port is read, the corresponding pin level is
read. Table 21.1 shows the function of PADR.
Rev. 1.00 Dec. 27, 2005 Page 787 of 932
Section 21 I/O Ports
REJ09B0269-0100