HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 184

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
3.6
3.6.1
Table 3.35 DSP Mode Extended System Control Instructions
Rev. 1.00 Dec. 27, 2005 Page 140 of 1044
REJ09B0269-0100
Instruction
SETRC #imm
SETRC Rn
LDRS @(disp,PC)
LDRE @(disp,PC)
STC MOD,Rn
STC RS,Rn
STC RE,Rn
STS DSR,Rn
STS A0,Rn
STS X0,Rn
STS X1,Rn
STS Y0,Rn
STS Y1,Rn
STS.L DSR,@-Rn
STS.L A0,@-Rn
STS.L X0,@-Rn
STS.L X1,@-Rn
STS.L Y0,@-Rn
STS.L Y1,@-Rn
STC.L MOD,@-Rn
STC.L RS,@-Rn
STC.L RE,@-Rn
LDS.L @Rn + ,DSR
LDS.L @Rn + ,A0
LDS.L @Rn + ,X0
LDS.L @Rn + ,X1
DSP Extended Function Instruction Set
CPU Extended Instructions
Instruction Code Operation
10000010iiiiiiii
0100nnnn00010100
10001100dddddddd
10001110dddddddd
0000nnnn01010010
0000nnnn01100010
0000nnnn01110010
0000nnnn01101010
0000nnnn01111010
0000nnnn10001010
0000nnnn10011010
0000nnnn10101010
0000nnnn10111010
0100nnnn01100010
0100nnnn01110010
0100nnnn10000010
0100nnnn10010010
0100nnnn10100010
0100nnnn10110010
0100nnnn01010011
0100nnnn01100011
0100nnnn01110011
0100nnnn01100110
0100nnnn01110110
0100nnnn10000110
0100nnnn10010110
imm→RC (of SR)
Rn[11:0] →RC(of SR)
(disp x 2 + PC) →RS
(disp x 2 + PC) →RE
MOD→Rn
RS→Rn
RE→Rn
DSR→Rn
A0→Rn
X0→Rn
X1→Rn
Y0→Rn
Y1→Rn
Rn-4→Rn, DSR→(Rn)
Rn-4→Rn, A0→(Rn)
Rn-4→Rn, X0→(Rn)
Rn-4→Rn, X1→(Rn)
Rn-4→Rn, Y0→(Rn)
Rn-4→Rn, Y1→(Rn)
Rn-4→Rn, MOD→(Rn)
Rn-4→Rn, RS→(Rn)
Rn-4→Rn, RE→(Rn)
(Rn) →DSR, Rn + 4→Rn
(Rn) →A0, Rn + 4→Rn
(Rn) →X0, Rn + 4→Rn
(Rn) →X1, Rn + 4→Rn
Execution
States
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
T Bit


























Category