HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 176

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
4. Overflow Mode: CS[2:0] = 011
5. Signed Greater Than Mode: CS[2:0] = 100
6. Signed Greater Than or Equal Mode: CS[2:0] = 101
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is
always cleared in this operation. So is the GT bit.
3.5.9
The PDMSB, most significant bit detection operation, is used to calculate the shift amount for
normalization. Figure 3.19 shows the PDMSB operation flow and table 3.28 shows the operation
definition. Table 3.29 shows the possible variations of this type of operation. The correspondence
between each operand and registers is the same as for ALU fixed-point operations, as shown in
table 3.21.
Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer
As shown in figure 3.19, the PDMSB operation uses all bits as a source operand, but the
destination operand is treated as an integer operation result because shift amount data for
normalization should be integer data as described in section 3.5.8, Shift Operations. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated, even though the specified condition is true, and the operation is executed. In case of an
unconditional operation, they are always updated with the operation result.
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The DC bit is set when the operation result is zero; otherwise it is cleared.
The DC bit is always cleared.
The DC bit is always cleared.
The DC bit is always cleared.
operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts.
When a register not providing the guard-bit parts is specified as a destination operand, the
upper word of the operation result is input into the destination register.
Most Significant Bit Detection Operation