HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 19

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.4
Section 10 Power-Down Modes ........................................................................295
10.1 Overview............................................................................................................................ 295
10.2 Register Descriptions ......................................................................................................... 298
10.3 Operation ........................................................................................................................... 302
Section 11 On-Chip Oscillation Circuits ...........................................................311
11.1 Overview............................................................................................................................ 311
11.2 Overview of CPG............................................................................................................... 313
11.3 Clock Operating Modes ..................................................................................................... 315
11.4 Register Description........................................................................................................... 320
11.5 Changing Frequency .......................................................................................................... 322
11.6 Overview of WDT ............................................................................................................. 323
11.7 Register Descriptions of WDT........................................................................................... 324
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.3.7
9.3.8
Usage Notes ....................................................................................................................... 292
10.1.1 Power-Down Modes ............................................................................................. 295
10.1.2 Reset ..................................................................................................................... 296
10.1.3 Input/Output Pins.................................................................................................. 298
10.2.1 Standby Control Register (STBCR)...................................................................... 298
10.2.2 Standby Control Register 2 (STBCR2)................................................................. 300
10.2.3 Standby Control Register 3 (STBCR3)................................................................. 301
10.3.1 Sleep Mode ........................................................................................................... 302
10.3.2 Software Standby Mode........................................................................................ 303
10.3.3 Module Standby Function..................................................................................... 305
10.3.4 STATUS Pin Change Timings.............................................................................. 306
11.1.1 Features................................................................................................................. 311
11.2.1 CPG Block Diagram ............................................................................................. 313
11.2.2 Input/Output Pins.................................................................................................. 315
11.4.1 Frequency Control Register (FRQCR) ................................................................. 320
11.5.1 Changing Multiplication Rate............................................................................... 322
11.5.2 Changing Division Ratio....................................................................................... 322
11.6.1 Block Diagram of WDT........................................................................................ 323
Flow of the User Break Operation ........................................................................ 281
Break on Instruction Fetch Cycle.......................................................................... 283
Break on Data Access Cycle................................................................................. 283
Break on X/Y-Memory Bus Cycle........................................................................ 285
Sequential Break ................................................................................................... 285
Value of Saved Program Counter ......................................................................... 286
PC Trace ............................................................................................................... 287
Usage Examples.................................................................................................... 287
Rev. 1.00 Dec. 27, 2005 Page xvii of xlii