HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 131

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

6. Program counter during repeat control
Table 3.7
Note: In table 3.7, the following labels are used.
RptDtct
RptDtct1 RptDtct1 + 4
RptDtct2 
RptDtct3 
If RC[11:0] ≥ 2, the program counter (PC) value is not correct for instructions two instructions
following a repeat detection instruction. In a repeat loop consisting of one to three instructions,
the PC indicates the correct value (instruction address + 4) for an instruction (repeat start
instruction) following a repeat detection instruction but the PC continues to indicate the same
address (repeat start instruction address) from the subsequent instruction to a repeat end
instruction. In a repeat loop consisting of four or more instructions, the PC indicates the correct
value (instruction address + 4) for an instruction following a repeat detec-tion instruction, but
PC indicates the RS and (RS +2) for instructions two and three instructions following the
repeat detection instruction. Here, RS indicates the value stored in the repeat start register
(RS). The correct operation cannot be guaranteed for the incorrect PC values.
Accordingly, PC relative addressing instructions placed two or more instructions following the
repeat detection instruction cannot be executed correctly and the correct results cannot be
obtained.
 PC relative addressing instructions
MOVA @(disp, PC), Rn
MOV.W @(disp, PC), Rn
MOV.L @(disp, PC), Rn
(Including the case when the MOV #imm,Rn is extended to MOV.W @(disp, PC), Rn or
MOV.L @(disp, PC), Rn)
RptDtct:
RptDtct1:
RptDtct2:
RptDtct3:
1
RptDtct + 4
PC Value during Repeat Control (When RC[11:0] ≥ 2)
An address of the repeat detection instruction
An address of the instruction one instruction following the repeat start
instruction (In a repeat loop consisting of one to three instructions, RptStart is
a repeat start instruction)
An address of the instruction two instruction following the repeat start
instruction
An address of the instruction three instruction following the repeat start
instruction
Number of Instructions in Repeat Loop
2
RptDtct + 4
RptDtct1 + 4
RptDtct1 + 4

3
RptDtct + 4
RptDtct1 + 4
RptDtct1 + 4
RptDtct1 + 4
Rev. 1.00 Dec. 27, 2005 Page 87 of 1044
Section 3 DSP Operating Unit
≥ 4
RptDtct +4
RptDtct1 + 4
RS
RS + 2
REJ09B0269-0100