HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 329

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.3.4
1. The break condition on an X/Y-memory bus cycle is specified only in channel B. If the XYE
2. When an X-memory address is selected as the break condition, specify an X-memory address
3. The timing of a data access break for the X memory or Y memory bus to occur is the same as a
9.3.5
1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break
2. In sequential break specification, the L/I/X/Y bus can be selected and the execution times
bit in BBRB is set to 1, the break address and break data on X/Y-memory bus are selected. At
this time, select the X-memory bus or Y-memory bus by specifying the XYS bit in BBRB. The
break condition cannot include both X-memory and Y-memory at the same time. The break
condition is applied to an X/Y-memory bus cycle by specifying L bus/data access/read or
write/word or no specified operand size in bits 7 to 0 in the break bus cycle register B (BBRB).
in the upper 16 bits in BARB and BAMRB. When a Y-memory address is selected, specify a
Y-memory address in the lower 16 bits. Specification of X/Y-memory data is the same for
BDRB and BDMRB.
data access break of the L bus. For details, see 5 in section 9.3.3, Break on Data Access Cycle.
condition matches after a channel A break condition matches. A user break is not generated
even if a channel B break condition matches before a channel A break condition matches.
When channels A and B conditions match at the same time, the sequential break is not issued.
To clear the channel A condition match when a channel A condition match has occurred but a
channel B condition match has not yet occurred in a sequential break specification, clear the
SEQ bit in BRCR to 0.
break condition can be also specified. For example, when the execution times break condition
is specified, the break condition is satisfied when a channel B condition matches with BETR =
H'0001 after a channel A condition has matched.
Break on X/Y-Memory Bus Cycle
Sequential Break
Rev. 1.00 Dec. 27, 2005 Page 285 of 932
Section 9 User Break Controller
REJ09B0269-0100