HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 295

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.4.4
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ5 to IRQ0.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
8.4.5
IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC and the SCIF0
are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit
7
6
5
4
3
2
1
0
Bit
7
Interrupt Request Register 0 (IRR0)
Interrupt Request Register 1 (IRR1)
Bit Name


IRQ5R
IRQ4R
IRQ3R
IRQ2R
IRQ1R
IRQ0R
Bit Name
TXI0R
Initial Value
0
0
0
0
0
0
0
0
Initial Value
0
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Reserved
These bit are always read as 0. The write value
should always be 0.
IRQn Interrupt Request
Indicates whether there is interrupt request input
to the IRQn pin. When edge-detection mode is
set for IRQn, an interrupt request is cleared by
writing 0 to the IRQnR bit after reading IRQnR =
1.
When level-detection mode is set for IRQn, an
interrupt request is set/cleared by only 1/0 input
to the IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
Legend: n = 0 to 5
Description
TXI0 Interrupt Request
Indicates whether the TXI0 (SCIF0) interrupt
request is generated.
0: TXI0 interrupt request is not generated
1: TXI0 interrupt request is generated
Rev. 1.00 Dec. 27, 2005 Page 251 of 932
Section 8 Interrupt Controller (INTC)
REJ09B0269-0100