HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 43

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Table 16.2
Table 16.3
Table 16.4
Table 16.5
Table 16.6
Section 17 Serial I/O with FIFO (SIOF)
Table 17.1
Table 17.2
Table 17.3
Table 17.4
Table 17.5
Table 17.6
Table 17.7
Table 17.8
Table 17.9
Table 17.10
Table 17.11
Table 17.12
Section 18 Ethernet Controller (EtherC)
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Table 18.5
Table 18.6
Section 20 Pin Function Controller (PFC)
Table 20.1
Table 20.2
Section 21 I/O Ports
Table 21.1
Table 21.2
Table 21.3
Table 21.4
Section 22 User Debugging Interface (H-UDI)
Table 22.1
Table 22.2
Table 22.3
Table 22.4
Relationship between n and Clock........................................................................ 553
SCSMR Settings for Serial Transfer Format Selection......................................... 560
SCSMR and SCSCR Settings for the SCIF Clock Source Selection .................... 560
Serial Transfer Formats......................................................................................... 562
The SCIF Interrupt Sources .................................................................................. 583
Pin Configuration.................................................................................................. 589
SIOF Serial Clock Frequency ............................................................................... 614
Serial Transfer Modes........................................................................................... 616
Frame Length........................................................................................................ 617
Audio Mode Specification for Transmit Data....................................................... 619
Audio Mode Specification for Receive Data ........................................................ 619
Setting for Number of Control Data Channels...................................................... 620
Conditions to Issue Transmit Request .................................................................. 622
Conditions to Issue Receive Request .................................................................... 622
Transmission and Reception Reset ....................................................................... 628
SIOF Interrupt Sources ......................................................................................... 629
Setting Condition of Transmit/Receive Interrupt Flag.......................................... 630
Pin Configuration.................................................................................................. 639
Transfer Frame Processing (Without CAM)......................................................... 711
Reception Frame Process...................................................................................... 713
Relay Frame Process (With CAM) ....................................................................... 713
Receive Frame Process (When External CAM Logic is Used)............................. 715
Relay Frame Process (When External CAM Logic is Used) ................................ 716
List of Multiplexed Pins (1).................................................................................. 779
List of Multiplexed Pins (2).................................................................................. 780
Port A Data Register (PADR) Read/Write Operations ......................................... 788
Port B Data Register (PBDR) Read/Write Operations (1) .................................... 789
Port B Data Register (PBDR) Read/Write Operations (2) .................................... 789
Port C Data Register (PCDR) Read/Write Operations.......................................... 790
Pin Configuration.................................................................................................. 792
H-UDI Commands................................................................................................ 794
This LSI’s Pins and Boundary Scan Register Bits................................................ 795
Reset Configuration .............................................................................................. 803
Rev. 1.00 Dec. 27, 2005 Page xli of xlii